1. Technical Field
The present invention relates to a semiconductor structure and a method of fabricating MOS device.
2. Description of Related Art
Metal oxide semiconductor field effect transistor (MOSFET) is a basic structure widely applied to various semiconductor devices such as memory devices, image sensors, and display devices. To meet the demand of lighter, thinner, and smaller electronic devices, the size of CMOS is continuously shrunk. Accompanying the miniaturization also comes various techniques for improving the carrier conductivity of the channel of a MOSFET. For example, for a silicon substrate, stress-generating regions may be formed at both sides of the gate structure on or in the substrate to produce so-called “strained Si channel.” The choice of stress-generating material for an N-channel or a P-channel generally differs, and thus the NMOS region and the PMOS region must be processed separately. As a result, the heights of the hard mask layer of the gate structure on the NMOS region and the hard mask layer of the gate structure on the PMOS region are different. To balance the height difference, an additional wet dip process is required, which in turn, may damage the gate material if the hard mask layer disposed at the top of the gate structure or the spacer disposed at the sidewalls of the gate structure does not have sufficient resistance against the etching solution of the wet dip process. It is therefore an important issue to select the material for the hard mask and the spacer.